1. Field of the Invention
The present invention relates to a level shifter circuit.
2. Description of the Related Art
When circuits operating with different power supply voltages are connected to each other, a level shifter circuit has been widely used and provided between the circuits. The level shifter circuit shifts the level of power supply voltage to ensure consistency. The level shifter circuit shifts up (or shifts down) the signal level of a former circuit so as to correspond to the signal level of a latter circuit side, and supplies the shifted-up (shifted-down) signal to the latter circuit.
For example, let us consider a case where a circuit operating with a low power supply voltage is connected to a circuit operating with a high power supply voltage. In this case, a level shifter circuit shifts up a signal from the low power supply voltage operating circuit side to a signal of the high power supply voltage level, and supplies the shifted-up signal to the high power supply voltage circuit side (See Japanese Laid-Open Patent Application JP-A-Heisei, 3-98314, for example).
FIG. 1 is a circuit diagram showing a configuration of a level shifter circuit described in Japanese Laid-Open Patent Application (JP-A-Heisei, 3-98314). In the level shifter circuit disclosed in the patent document, an active device for receiving a digital signal on the low-voltage side consists of a first MOS transistor 101 and a second MOS transistor 102. The digital signal and the inverted digital signal on the low-voltage side are input to respective gates of the first MOS transistor 101 and the second MOS transistor 102. A third MOS transistor 103 and a fourth MOS transistor 104 of the opposite conductive type are interposed between the high power supply line VDD and respective output sides of the first MOS transistor 101 and the second MOS transistor 102. Also, respective gates of the third MOS transistor 103 and the fourth MOS transistor 104 are connected to respective output sides of the second MOS transistor 102 and the first MOS transistor 101. A digital signal on the high-voltage side is taken from an output terminal 107 connected to the output side of the second MOS transistor 102. According to the level shifter circuit thus constructed, it is possible to supply the signal output from the low power supply voltage operating circuit to the high power supply voltage operating circuit.
For example, let us consider a case when an input signal to an input signal terminal 105 changes from High level to Low level, and an input signal to the, other input signal terminal 106 changes from Low level to High level. In this case, the N-channel MOS transistor 102 is turned on, and then the P-channel MOS transistor 103 is turned on. Thus, two steps are necessary for the change in the voltage level at a node 111 from Low level to High level according to the above-mentioned conventional configuration. On the other hand, let us consider a case when an input signal to the input signal terminal 105 changes from Low level to High level, and an input signal to the other input signal terminal 106 changes from High level to Low level. Similar to the foregoing case, two steps are necessary for the change in the voltage level at a node 112 from Low level to High level. As described above, a high-speed operation is difficult according to the conventional level shifter shown in FIG. 1.
Techniques to accelerate an operation of a level shifter circuit are known. A level shifter circuit described in Japanese Laid-Open Patent Application (JP-A-Heisei, 7-193488) has a first N-channel MOS transistor and a second N-channel MOS transistor. A drain of the first N-channel MOS transistor is connected to a high voltage power supply. A gate of the first N-channel MOS transistor is connected to an output of an inverter operating with a low power supply voltage. A source of the first N-channel MOS transistor is connected to a drain of a first P-channel MOS transistor of two P-channel MOS transistors, a gate of a second P-channel MOS transistor, and a drain of the second N-channel MOS transistor. A source of the second N-channel MOS transistor is connected to a gate of the first P-channel MOS transistor, a drain of the second P-channel MOS transistor and a drain of the first N-channel MOS transistor.
The Japanese Laid Open Patent Application (JP-P2003-143004A) describes a technique capable of realizing reduction in static power supply current and operation time while restricting an increase of the circuit area in a chip. According to the technique described in the patent document, when a low power supply voltage operation circuit and a high power supply voltage operation circuit as circuits operating with different power supply voltages are connected to each other, provided between the power supply voltage operation circuits is a first N-channel MOS transistor which is turned of/off in sync with level change of a signal from one power supply voltage operation circuit. Furthermore, a second N-channel MOS transistor which is turned on/off in inverse to the level change of the signal from the one power supply voltage operation circuit side, a first P-channel MOS transistor which is turned on/off in sync with the second N-channel MOS transistor and a second P-channel MOS transistor which is turned on/off in sync with the first N-channel MOS transistor are serially connected from power supply voltage of the other power supply voltage operation circuit side to a ground potential through the first P-channel MOS transistor and the first N-channel MOS transistor.
Simultaneously, they are serially connected from power supply voltage of the other power supply voltage operation circuit side to the ground potential through the second P-channel MOS transistor and the second N-channel MOS transistor. A signal from a first connection point between the first P-channel MOS transistor and the first N-channel MOS transistor or a second connection point between the second P-channel MOS transistor and the second N-channel MOS transistor is transmitted to the other power supply voltage operation circuit side through a buffer operating with the power supply voltage of the other power supply voltage operation circuit. Thus, between the power supply voltage operation circuits, the voltage level of the signal from the one power supply voltage operation circuit side is shifted to match with the voltage level of the signal from the other power supply voltage operation circuit side. In the level shifter circuit, provided are a first diode which is connected to a substrate terminal of the first N-channel MOS transistor at an anode thereof and connected to the second connection point at a cathode thereof, and a second diode which is connected to a substrate terminal of the second N-channel MOS transistor at an anode thereof and connected to the first connection point at a cathode thereof.